 Products
> Optima |
 |
|
 |
|
 |
PadOptima is an optimal pad configuration solution
to minimize painful and time-consuming pad
configuration process including pad sequence editing and power pad assignment to prevent the excessive voltage drop in core area and the excessive simultaneous output
switching noise in signal IO pad area.
PadOptima provides a rich set of IO pad
planning utilities. Typical pad configuration flow consists of importing the
pad information, pad placement, power ring connectivity extraction, pad
design rule check, and validation of power group on the ring.
|
|
 |
|
| |
 |
| |
| PadOptima helps you create or modify an IO pad row based on the user input or automatic setup, and provides a flexible pad row design such as stacked IO row and area IO row so that you can perform an optimal design against the environment with a number of pads and the limited chip size. It also helps relocate or create a pad or a group of pads on the pad row with graphical visualization.
|
| |
 |
| |
| There are many design rules for a good pad configuration to guarantee the performance of the IO pads. The connectivity check for each pad is very useful to validate the proper grouping of IO pads which
share the common power pad ring and to analyze the simultaneous switching noise (SSN).
|
| |
 |
| |
| The power net connectivity of each pad can be estimated by the pad sequence and the location of slot cells which have the breaking information of pad ring of each power net. The problematic ring segment which is electrically open or short can be detected by evaluating the power ring segment. The power net sharing information is also used for the SSN analysis. PadOptima helps you check the power groups and pad instances on the power ring in graphical and effective manner to re-design the pad rings easily by relocating any pad instances or redefining power groups with minimum change in chip size.
|
| |
 |
| |
 |
| |
| PadOptima provides an efficient method to calculate the optimal number and location of IO power pads, which is based on a simple but accurate model considering the effects of parasitic elements of package and bond wire, and also provides the environment to debug SSN. These features enable you to save the package pins contributing to cost reduction. PadOptima provides a SPICE simulation input file. This helps you check the dependence of the switching noise on the parasitic and evaluate different conditions through what-if analysis.
|
| |
 |
| |
| PadOptima provides an efficient pad assignment to optimize the number and location of the power/ground pads to meet the requirements such as target IR-drop and pad current limit on the power
distribution network. It also helps you analyze and validate the results with voltage map and IR-drop
sensitivity check, and finally decide the proper number of the pads for the given resources.
|
| |
 |
| |
| PadOptima provides RDL routability check capability to predict the package design problem in early
design stage. It recognizes the predefined bump pads as routing obstacles and checks the routability for all I/O signals. The routing results can be checked with graphic user interface. Usually the RDL routing problems can be found in the last step of SOC design and it is very time-consuming and painful work to fix the problems.
|
| |
 |
| |
| PadOptima provides a connectivity editing feature which creates logical connection between BGA and IO pads. The result can be used for the 3rd party PCB design tools.
|
|
