Products > Pillar-DP¢ç-Navis
esl design
The lack of information sharing between resister transfer level (RTL) designers and IC implementation designers causes unexpected design iterations in leading edge system-on-chip (SOC) design, and results in time-to-market (TTM) delay if there is no proper design automation solution. Entasys develops and delivers industry proven pre-RTL design planning solution, Navis, to fill the technology gap between system level design and IC implementation. Navis enables you to predict and prevent the physical implementation problems in pre-RTL design stage.
 
dot Generates RTL schematic to visualize the logical
circuit of design with RTL components.
dot Verifies the floating nets, unconnected pins, and
unresolved instances
dot Supports cross-probing between schematic and RTL
netlist.
dot Finds the clock net by tracing back clock signal from
the flip-flops.
dot Estimates the gate count of each module through
ware inference using generic cell library.
 
 
Navis considers the power intent through the standard power format interface or the creation of the power scenario by using the power and clock modes. And also it takes the process technology into account.
 
 
dot Provides the automatic placement of blocks considering power/clock domain and cluster information.
dot Provides the automatic placement of hard-macros on their parent module according to their
hierarchy dependency.
dot Provides hierarchical placement of clusters according to their hierarchy dependency
dot Provides mixed mode placement for macros and primitive cells
dot Analyzes the routing congestion and inter-block net delay
dot Provides the advanced IO planning for complex IO pad configuration such as Stacked or Area IO.
dot Estimates the chip size considering floorplanning constraints and power routing scheme.
dot Finds the optimal geometric configuration of power and ground pads to meet the requirement of
IR-drop and electro-migration.
dot Synthesizes the power network based on efficient and accurate rail resource estimation and
analyzes it based on the power scenario.
dot Validates the IR-drop specification for each power scenario.
dot Predicts the package design problem at early stage by checking RDL routability and BGA
connectivity.
 
 
dot Estimates the routing congestion and the interconnect performance to evaluate floorplan quality.
dot Helps system architect with pin assignment for hierarchical design.
 
 
dot Links logic synthesis and physical implementation