Ventus is a new conceptual design entry solution to estimate the power and area of the design in micro-architecture level. At the early stage of system-on-chip (SOC) design, a lot of unknown - design parameters make it difficult to estimate the power consumption and area of the chip accurately.
As the complexity of the SOC design is increasing and the demand for low power design technique is growing, the more design constraints including process technology parameters and physical layout design parameters should be considered in power and area estimation.
Ventus begins with specifying a system-level specification of a SOC design, which is information on a given process technology, defining number of IO pins with pad assignment, describing clock/power domains, and identifying the SOC blocks such as hard/soft macros and memory. Most of this information may be delivered from existing floorplan, previous project or initial design
specification. The more detailed information you put in, the more accurate result you can get.
Design entry with block level specification Design constraint creation Chip level floorplanning Floorplan based area esitmation Chip level peak power estimation Initial block placement Advanced IO Pad configuration. Power pad optimization Yield estimation What-if analysis Estimation report review
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Design entry with block level specification
